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STE2004SDIE2 Datasheet(PDF) 10 Page - STMicroelectronics |
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STE2004SDIE2 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 79 page  Circuit description STE2004S 10/79 the master configuration. The only recognized configuration is Vop=0 that forces the charge pump to be in off state whatever is the value of Vsense_aux. To synchronize the master and slave timing circuits, the slave driver FR_IN pad must be connected to master driver FR_OUT pad, and slave driver OSC_IN pad must be connected to the master driver OSC_OUT Pad ( Figure 4.). This connection ensures a synchronization at both frame level (R0 on the master is driven together with the Slave R0 driver) and at oscillator level (same frame frequency on the master and on the slave). If the synchronization at frame level is not required, FR_IN pin must be connected toVDD1 or to VDD1_aux ( Figure 5.). During the power up procesure, the master device must be forced to exit from power down before the slave device. To enter into PowerDown mode, the slave device must be forced into power down state before master device. Figure 4. Master slave logic connection with frame synchronization Figure 5. Master slave logic connection without frame synchronization 3.5 Bias levels To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established according to the following ( Figure 6.) OSCOUT LR0219 STE2004S VDD1AUX STE2004S FROUT OSCIN FRIN OSCIN FRIN OSCOUT FROUT OSCOUT LR0220 STE2004S VDD1AUX STE2004S FROUT OSCIN FRIN OSCOUT FROUT VDD1AUX OSCIN FRIN V LCD n3 + n4 + ------------- V LCD , n2 + n4 + ------------- V LCD , 2 n4 + ------------- V LCD , 1 n4 + ------------- V LCD ,V SS , |
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