ISSUE 1.5 : April 2001

SYS88000RKX - 85/10/12

4

Write Cycle

-85

-10

-12

Parameter

Symbol

min

max

min

max

min

max

Unit

Write Cycle Time

t

WC

85

-

100

-

120

-

ns

Chip Selection to End of Write

t

CW

75

-

80

-

100

-

ns

Address Valid to End of Write

t

AW

75

-

80

-

100

-

ns

Address Setup Time

t

AS

0-

0-

0

-

ns

Write Pulse Width

t

WP

60

-

70

-

70

-

ns

Write Recovery Time

t

WR

5-

5-

5

-

ns

Write to Output in High Z

***

t

WHZ

035

0

40

0

40

ns

Data to Write Time Overlap

t

DW

40

-

45

-

45

-

ns

Data Hold from Write Time

t

DH

0-

0-

0

-

ns

Output active from end of write ***

t

OW

5-

5-

5

-

ns

*** Theses signals are the internal Ram signals on the module and are included to assist control signal

timing.

-85

-10

-12

Parameter

Symbol

min

max

min

max

min

max

Unit

Read Cycle Time

t

RC

85

-

100

-

120

-

ns

Address Access Time

t

AA

-

85

-

100

-

120

ns

Chip Select Access Time

t

ACS

-

85

-

100

-

120

ns

Output Enable to Output Valid

t

OE

-50-55

-60

ns

Output Hold from Address Change

t

OH

11.5

-

11.5

-

11.5

-

ns

Chip Selection to Output in Low Z

t

CLZ

1.5

-

1.5

-

1.5

-

ns

Output Enable to Output in Low Z

t

OLZ

1.5

-

1.5

-

1.5

-

ns

Chip Deselection to O/P in High Z

t

CHZ

050505

ns

Output Disable to Output in High Z

t

OHZ

050505

ns

Read Cycle

AC OPERATING CONDITIONS