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TLV990B Datasheet(PDF) 6 Page - Texas Instruments

Part No. TLV990B
Description  3-V, 10-BIT, 28-MSPS AREA CCD AND VIDEO SIGNAL PROCESSOR
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TLV990B
3-V, 10-BIT, 28-MSPS AREA CCD AND VIDEO SIGNAL PROCESSOR
SLAS327– FEBRUARY 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, TA = 25°C,
AVDD=DVDD=3 V, ADCCLK=28 MHz (unless otherwise noted)
user digital-to-analog converters (DAC)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC resolution
8
Bits
INL
Integral nonlinearity
±0.75
LSB
DNL
Differential nonlinearity
±0.5
LSB
Output voltage range
Assured by design
0
VDD
V
Output settling time
10 pF external load, settle to 1 mV
4
µs
reference voltages
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal bandgap voltage reference
1.43
1.50
1.58
V
Temperature coefficient
100
ppm/
°C
ADC Ref+
Externally decoupled
2
V
ADC Ref–
Externally decoupled
1
V
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Logic inputs
IIH
High-level input current
DIVDD =3V
–10
10
µA
IIL
Low-level input current
DIVDD = 3 V
–10
10
µA
Ci
Input capacitance
5
pF
Logic outputs
VOH
High-level output voltage
IOH = 50 µA, DIVDD = 3 V
DIVDD–0.4
V
VOL
Low-level output voltage
IOL = 50 µA, DIVDD = 3 V
0.4
V
IOZ
High-impedance-state output current
±10
µA
Co
Output capacitance
5
pF
key timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSRW
SR pulse width
Measured at 50% of pulse height
10
ns
tSVW
SV pulse width
Measured at 50% of pulse height
10
ns
tOD
ADCCLK-to-output data delay
6
ns
tCSF
CS falling edge to SCLK rising edge
0
ns
tCSR
SCLK falling edge to CS rising edge
5
ns




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