LAN9211-ABZJ datasheet(30/144 Pages) SMSC

Part #	LAN9211-ABZJ

Description	High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX

Download	144 Pages

Scroll/Zoom	100%

Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

Logo

30 / 144 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX

Datasheet

Revision 1.8 (06-06-07)

30

SMSC

LAN9211

DATASHEET

3.6.2

Transmit Checksum Offload Engine (TXCOE)

The transmit checksum offload engine provides assistance to the CPU by calculating a 16-bit

checksum, typically for TCP, for a transmit Ethernet frame. The TXCOE calculates the checksum and

inserts the results back into the data stream as it is transferred to the MAC.

To activate the TXCOE and perform a checksum calculation, the host must first set the TX checksum

offload engine enable bit (TXCOE_EN) in the COE_CR—Checksum Offload Engine Control Register.

The host then pre-pends a 3 DWORD buffer to the data that will be transmitted. The pre-pended buffer

includes a TX Command ‘A’, TX Command ‘B’, and a 32-bit TX checksum preamble. When bit 14 (CK)

of the TX Command ‘B’ is set in conjunction with bit 13 (FS) of TX Command ‘A’ and bit 16

(TXCOE_EN) of the COE_CR register, the TXCOE will perform a checksum calculation on the

associated packet. When these three bits are set, a 32-bit TX checksum preamble must be pre-pended

to the beginning of the TX packet (refer to Table 3.7). The TX checksum preamble instructs the TXCOE

on the handling of the associated packet. Bits 11:0 of the TX checksum preamble define the byte offset

at which the data checksum calculation will begin (TXCSSP). The checksum calculation will begin at

this offset and will continue until the end of the packet. The data checksum calculation must not begin

in the MAC header (first 14 bytes) or in the last 4 bytes of the TX packet. When the calculation is

complete, the checksum will be inserted into the packet at the byte offset defined by bits 27:16 of the

TX checksum preamble (TXCSLOC). The TX checksum cannot be inserted in the MAC header (first

14 bytes) or in the last 4 bytes of the TX packet. If the CK bit is not set in the first TX Command ‘B’

of a packet, the packet is passed directly through the TXCOE without modification, regardless if the

TXCOE_EN is set. An example of a TX packet with a pre-pended TX checksum preamble can be

found in Section 3.12.6.3, "TX Example 3". In this example the host writes the packet data to the

ethernet controller in four fragments, the first containing the TX Checksum Preamble. Figure 3.17

shows how these fragments are loaded into the TX Data FIFO. For more information on the TX

Command ‘A’ and TX Command ‘B’, refer to Section 3.12.2, "TX Command Format".

If the TX packet already includes a partial checksum calculation (perhaps inserted by an upper layer

protocol), this checksum can be included in the hardware checksum calculation by setting the TXCSSP

field in the TX checksum preamble to include the partial checksum. The partial checksum can be

replaced by the completed checksum calculation by setting the TXCSLOC pointer to point to the

location of the partial checksum.

Note: When the TXCOE is enabled, the third DWORD of the pre-pended packet is not transmitted.

However, 4 bytes must be added to the packet length field in TX Command ‘B’.

Note: When the TXCOE is enabled, the store and forward mode must be enabled (bit 20 (SF) of the

HW_CFG—Hardware Configuration Register must be set).

Table 3.7 TX Checksum Preamble

FIELD

DESCRIPTION

31:28

RESERVED

27:16

TXCSLOC - TX Checksum Location

This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The

checksum will replace two bytes of data starting at this offset.

Note:

The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4

bytes of the TX packet.

15:12

RESERVED

11:0

TXCSSP - TX Checksum Start Pointer

This field indicates start offset, in bytes, where the checksum calculation will begin in the associated

TX packet.

Note:

The data checksum calculation must not begin in the MAC header (first 14 bytes) or in

the last 4 bytes of the TX packet.

Similar Part No. - LAN9211-ABZJ

Manufacturer	Part #	Datasheet	Description
SMSC Corporation	LAN9211-ABZJ	1Mb / 147P	High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

More results

Similar Description - LAN9211-ABZJ

Manufacturer	Part #	Datasheet	Description
SMSC Corporation	LAN9211_0711	1Mb / 146P	High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
	LAN9210	4Mb / 146P	Small Form Factor Single- Chip Ethernet Controller with HP Auto-MDIX
	LAN9211	1Mb / 147P	High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
	LAN9210	2Mb / 147P	Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
	LAN9218	1Mb / 130P	High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX
	LAN9218	1Mb / 133P	High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX
	LAN9218	1Mb / 134P	High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
	LAN9217	1Mb / 134P	16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
	LAN9217	1Mb / 137P	16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
	LAN9217	1Mb / 139P	16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support

More results

LAN9211-ABZJ Datasheet(PDF) 30 Page - SMSC Corporation

LAN9211-ABZJ Datasheet(HTML) 30 Page - SMSC Corporation

Similar Part No. - LAN9211-ABZJ

Similar Description - LAN9211-ABZJ

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL