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PI7C9X130 Datasheet(PDF) 30 Page - Pericom Semiconductor Corporation |
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PI7C9X130 Datasheet(HTML) 30 Page - Pericom Semiconductor Corporation |
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30 / 157 page  PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE Page 30 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2 Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode Secondary Bus Configuration Access for Non- Transparent Mode only Transparent Mode (type1) Non- Transparent Mode (Type0) EEPROM (I2C) Access SM Bus Access 0Eh 4Eh Header Type Register Header Type Register No Yes 0Fh 4Fh Reserved Reserved - - 13h – 10h 53h – 50h Reserved Primary CSR and Memory 0 BAR No Yes 17h – 14h 57h – 54h Reserved Primary CSR I/O BAR No Yes 18h 58h Primary Bus Number Register Downstream I/O or Memory 1 BAR No Yes 19h 59h Secondary Bus Number Register Downstream I/O or Memory 1 BAR No Yes 1Ah 5Ah Subordinate Bus Number Register Downstream I/O or Memory 1 BAR No Yes 1Bh 5Bh Secondary Latency Timer Downstream I/O or Memory 1 BAR No Yes 1Ch 5Ch I/O Base Register Downstream Memory 2 BAR No Yes 1Dh 5Dh I/O Limit Register Downstream Memory 2 BAR No Yes 1Fh – 1Eh 5Fh – 5Eh Secondary Status Register Downstream Memory 2 BAR No Yes 21h – 20h 61h – 60h Memory Base Register Downstream Memory 3 BAR No Yes 23h – 22h 63h – 62h Memory Limit Register Downstream Memory 3 BAR No Yes 25h – 24h 65h – 64h Prefetchable Memory Base Register Downstream Memory 3 Upper 32-bit BAR No Yes 27h – 26h 67h - 66h Prefetchable Memory Limit Register Downstream Memory 3 Upper 32-bit BAR No Yes 2Bh – 28h 2Bh – 28h Prefetchable Memory Base Upper 32-bit Register Reserved No Yes 2Dh – 2Ch 2Dh – 2Ch Prefetchable Memory Limit Upper 32-bit Register Subsystem Vendor ID Yes 2 Yes 5 2Fh – 2Eh 2Fh – 2Eh Prefetchable Memory Limit Upper 32-bit Register Subsystem ID Yes 2 Yes 5 31h – 30h 31h – 30h I/O Base Upper 16-bit Register Reserved No Yes 33h – 32h 33h – 32h I/O Limit Upper 16-bit Register Reserved No Yes |
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