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PI7C9X130 Datasheet(PDF) 37 Page - Pericom Semiconductor Corporation |
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PI7C9X130 Datasheet(HTML) 37 Page - Pericom Semiconductor Corporation |
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37 / 157 page  PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE Page 37 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2 PCI Express / PCI Memory Offset SM Bus Offset Register Name Reset Value EEPROM (I2C) Access SM Bus Access 1FFh – 100h 3FFh – 300h Upstream Memory 2 Lookup Table 0 No Yes FFFh – 200h 11FFh – 400h Reserved 0 No Yes 7.4 PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE The following section describes the configuration space when the device is in transparent mode. The descriptions for different register type are listed as follow: Register Type Descriptions RO Read Only ROS Read Only and Sticky RW Read/Write RWC Read/Write “1” to clear RWS Read/Write and Sticky RWCS Read/Write “1” to clear and Sticky 7.4.1 VENDOR ID – OFFSET 00h Bit Function Type Description 15:0 Vendor ID RO Identifies Pericom as the vendor of this device. Returns 12D8h when read. 7.4.2 DEVICE ID – OFFSET 00h Bit Function Type Description 31:16 Device ID RO Identifies this device as the PI7C9X130. Returns E130 when read. 7.4.3 COMMAND REGISTER – OFFSET 04h Bit Function Type Description 0 I/O Space Enable RW 0: Ignore I/O transactions on the primary interface 1: Enable response to memory transactions on the primary interface Reset to 0 1 Memory Space Enable RW 0: Ignore memory read transactions on the primary interface 1: Enable memory read transactions on the primary interface Reset to 0 2 Bus Master Enable RW 0: Do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the bridge to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface. If the primary of the reverse bridge is PCI-X mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0 |
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Similar Description - PI7C9X130 |
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