 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PC912XDP512F0CPV Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc |
|
||||||||||||||||||||||||||||||
PC912XDP512F0CPV Datasheet(HTML) 52 Page - Freescale Semiconductor, Inc |
|
|
52 / 1350 page  Chapter 1 Device Overview MC9S12XD-Family MC9S12XDP512 Data Sheet, Rev. 2.17 52 Freescale Semiconductor 1.2.2 Signal Properties Summary Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts of the S12XD, S12XB and S12XA family please refer to Appendix E Derivative Differences. Table 1-7. Signal Properties Summary (Sheet 1 of 4) Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 Power Supply Internal Pull Resistor Description CTRL Reset State EXTAL — — — — VDDPLL NA NA Oscillator pins XTAL — — — — VDDPLL NA NA RESET — — — — VDDR PULLUP External reset TEST — — — — N.A. RESET pin DOWN Test input VREGEN — — — — VDDX PUCR Up Voltage regulator enable Input XFC — — — — VDDPLL NA NA PLL loop filter BKGD MODC — — — VDDX Always on Up Background debug PAD[23:08] AN[23:8] — — — VDDA PER0/ PER1 Disabled Port AD I/O, Port AD inputs of ATD1 and analog inputs of ATD1 PAD[07:00] AN[7:0] — — — VDDA PER1 Disabled Port AD I/O, Port AD inputs of ATD0 and analog inputs of ATD0 PA[7:0] — — — — VDDR PUCR Disabled Port A I/O PB[7:0] — — — — VDDR PUCR Disabled Port BI/O PA[7:0] ADDR[15:8] IVD[15:8] — — VDDR PUCR Disabled Port A I/O, address bus, internal visibility data PB[7:1] ADDR[7:1] IVD[7:0] — — VDDR PUCR Disabled Port B I/O, address bus, internal visibility data PB0 ADDR0 UDS VDDR PUCR Disabled Port B I/O, address bus, upper data strobe PC[7:0] DATA[15:8] — — — VDDR PUCR Disabled Port C I/O, data bus PD[7:0] DATA[7:0] — — — VDDR PUCR Disabled Port D I/O, data bus PE7 ECLKX2 XCLKS — — VDDR PUCR Up Port E I/O, system clock output, clock select PE6 TAGHI MODB — — VDDR While RESET pin is low: down Port E I/O, tag high, mode input PE5 RE MODA TAGLO — VDDR While RESET pin is low: down Port E I/O, read enable, mode input, tag low input PE4 ECLK — — — VDDR PUCR Up Port E I/O, bus clock output PE3 LSTRB LDS EROMCTL — VDDR PUCR Up Port E I/O, low byte data strobe, EROMON control PE2 R/W WE — — VDDR PUCR Up Port E I/O, read/write PE1 IRQ — — — VDDR PUCR Up Port E Input, maskable interrupt |
Similar Part No. - PC912XDP512F0CPV |
|
Similar Description - PC912XDP512F0CPV |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
