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SN65LVDT41PWR Datasheet(PDF) 2 Page - Texas Instruments |
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SN65LVDT41PWR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 16 page www.ti.com TYPICAL MEMORY STICK INTERFACE EXTENSION 1Y 1Z 1D 1A 1B 5Y 5Z 1R 5D 2Y 2Z 2D 2A 2B 2R 3Y 3Z 3D 3A 3B 3R 4Y 4Z 4D 4A 4B 4R 5A 5B 5R SCLK BS DIR SD1 SD2 CBT SCLK BS SDIO Memory Stick CBT SCLK BS SDIO DIR Memory Stick Host Controller SN65LVDT41 SN65LVDT14 ABSOLUTE MAXIMUM RATINGS PACKAGE DISSIPATION RATINGS SN65LVDT14 SN65LVDT41 SLLS530B – APRIL 2002 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. over operating free-air temperature range unless otherwise noted(1) SN65LVDT14, UNIT SN65LVDT41 Supply voltage range(2) VCC -0.5 to 4 V D or R -0.5 to 6 V Input voltage range A, B, Y, or Z -0.5 to 4 V Human body model(3), A, B, Y, Z, and GND ±16 KV Electrostatic discharge Human body model(3), all pins ±8 KV Charged device model(4), all pins ±500 V Continuous total power dissipation See Dissipation Rating Table Storage temperature range -65 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. TA <25°C OPERATING FACTOR TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING PW 774 mW 6.2 mW/°C 402 mW 2 Submit Documentation Feedback |
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