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S29WS256P0LBFW002 Datasheet(PDF) 10 Page - SPANSION

Part # S29WS256P0LBFW002
Description  MirrorBit짰 Flash Family 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
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S29WS-P
S29WS-P_00_A11 September 28, 2007
Da ta
Sh e e t
2.
Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Type
Description
AMAX–A0
Input
Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and
22 for WS128P)
DQ15–DQ0
I/O
Data input/output.
CE#
Input
Chip Enable. Asynchronous relative to CLK.
OE#
Input
Output Enable. Asynchronous relative to CLK.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply
VCCQ
Supply
Device Input/Output Power Supply (Must be ramped simultaneously with VCC)
VSS
Supply
Ground.
NC
No Connect
Not connected internally.
RDY
Output
Ready. Indicates when valid burst data is ready to be read.
CLK
Input
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at VIL or VIH while in asynchronous mode.
AVD#
Input
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at
VIH for all other conditions.
ACC
Input
Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
RFU
Reserved
Reserved for future use (see MCP look-ahead pinout for use with MCP).


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