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LAN9218 Datasheet(PDF) 29 Page - SMSC Corporation |
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LAN9218 Datasheet(HTML) 29 Page - SMSC Corporation |
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29 / 133 page  High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Datasheet SMSC LAN9218 29 Revision 1.8 (06-06-07) DATASHEET 3.6.2 16-bit Bus Writes The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit write). No ordering requirements exist. The processor can access either the low or high word first, as long as the next write is performed to the other word. If a write to the same word is performed, the LAN9218 disregards the transfer. 3.6.3 16-bit Bus Reads The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit read). No ordering requirements exist. The processor can access either the low or high word first, as long as the next read is performed from the other word. If a read to the same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The LAN9218 will reset its read counters and restart a new cycle on the next read. The Upper 16 data pins (D[31:16]) are not driven by the LAN9218 in 16-bit mode. These pins have internal pull-down’s and the signals are left in a high-impedance state. 3.6.4 Big and Little Endian Support The LAN9218 supports “Big-” or “Little-Endian” processors with either 16 or 32-bit busses. To support big-endian processors, the hardware designer must explicitly invert the layout of the byte lanes. 3.6.5 Word Swap Function Internally the LAN9218 is 32-bits wide. The LAN9218 supports a Word Swap Function when its Host Bus Interface is configured to operate in 16-bit mode. This feature is controlled by the Word Swap Register, which is described in Section 5.3.17, "WORD_SWAP—Word Swap Control," on page 87. This register affects how words on the data bus are written to or read from the Control and Status Registers and the Transmit and Receive Data/Status FIFOs. Refer to Table 3.7, "Word Swap Control (16-bit mode only)" below for more details. Whenever the LAN9218 transmits data from the Transmit Data FIFO to the network, the low order word is always transmitted first, and when the LAN9218 receives data from the network to the Receive Data FIFO, the low-order word is always received first. This register only takes effect when the LAN9218 is configured to operate in 16-bit mode. In 32-bit mode, this register is ignored and the upper data bits, D[31:16], are always mapped to the high-order word, and the lower data bits, D[15:0] are always mapped to the low-order word. Table 3.7 Word Swap Control (16-bit mode only) ADDRESS A1 PIN BYTE ORDER DESCRIPTION D[15:8] D[7:0] Default Mode - Word Swap Register equal to 0x00000000 or any value other than 0xFFFFFFFF A1 = 0 Byte 1 Byte 0 When A1=0, D[15:0] is mapped to the low order words of CSRs and FIFOs. When A1=1, D[15:0] is mapped to the high-order words of CSRs and FIFOs. Since low-order words are always transmitted/received first, A1=0 data will always precede A1=1 data. A1 = 1 Byte 3 Byte 2 Word Swap Mode - Word Swap Register equal to 0xFFFFFFFF A1 = 0 Byte 3 Byte 2 When A1=0, D[15:0] is mapped to the high order words of CSRs and FIFOs. When A1=1, D[15:0] is mapped to the low order words of CSRs and FIFOs. In this case A1=1 data will always precede A1=0 data. A1 = 1 Byte 1 Byte 0 |
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