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LAN9218 Datasheet(PDF) 20 Page - SMSC Corporation |
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LAN9218 Datasheet(HTML) 20 Page - SMSC Corporation |
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20 / 133 page  High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Datasheet Revision 1.8 (06-06-07) 20 SMSC LAN9218 DATASHEET Note 2.1 Please refer to the SMSC application note AN14.10 - “Migrating from LAN9118 to the LAN9218I” for additional details. 2.1 Buffer Types 3,65 Core Voltage Decoupling VDD_CORE P 2 +1.8 V from internal core regulator. Both pins must be connected together externally. Each pin requires a 0.01uF decoupling capacitor. In addition, pin 3 requires a bulk 10uF capacitor (<2 Ohm ESR) in parallel. See Note 2.1. 1,66 Core Ground GND_CORE P 2 Ground for internal digital logic 7 PLL Power VDD_PLL P 1 +1.8V Power from the internal PLL regulator. This pin must be connected to a 10uF capacitor (<2 Ohm ESR), in parallel with a 0.01uF capacitor to ground. See Note 2.1. 4 PLL Ground VSS_PLL P 1 GND for the PLL 8 Reference Power VDD_REF P 1 Connected to 3.3v power and used as the reference voltage for the internal PLL 11 Reference Ground VSS_REF P 1 Ground for internal PLL reference voltage Table 2.6 Buffer Types TYPE DESCRIPTION I Input pin IS Schmitt triggered Input O12 Output with 12mA sink and 12mA source OD12 Open-drain output with 12mA sink IO8 I/O with 8mA symmetrical drive OD8 Open-drain output with 8mA sink O8 Output 8mA symmetrical drive PU 50uA (typical) internal pull-up PD 50uA (typical) internal pull-down AI Analog input AO Analog output Table 2.5 System and Power Signals (continued) PIN NO. NAME SYMBOL BUFFER TYPE NUM PINS DESCRIPTION |
Similar Part No. - LAN9218 |
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Similar Description - LAN9218 |
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