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W83195BG-101 Datasheet(PDF) 17 Page - Winbond |
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W83195BG-101 Datasheet(HTML) 17 Page - Winbond |
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17 / 27 page  W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS Publication Release Date: March 2006 - 13 - Revision 0.7 Table-2 CPU, SRC, PCI divider ratio selection Table CPU Bit1, 0 LSB MSB 00 01 10 11 0 Div2 Div3 Div4 Div6 Bit2/ Bit4/ Bit6 1 Div0 Div0 Div0 Div0 7.14 Register 13: Step-less Enable Control (Default: 0Fh) BIT NAME PWD DESCRIPTION TYPE 7 EN_MN_PROG 0 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<2:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). R/W 6 N<10> 0 Programmable N divisor bit 10. R/W 5 Reserved 0 Reserved R/W 4 Reserved 0 Reserved R/W 3 IVAL<3> 1 R/W 2 IVAL<2> 1 R/W 1 IVAL<1> 1 R/W 0 IVAL<0> 1 Charge pump current selection R/W |
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