June 19, 2007 S71GL-N_00_02

S71GL-N Based MCPs

7

Da ta

Sh e e t

(Adv a n ce

In f o r m ation)

4.

Pin Description

Pin

Description

A21–A0

22 Address Inputs (Common and Flash only) (A20-A0 for the S71GL032N)

DQ15–DQ0

16 Data Inputs/Outputs (Common)

CE1#f

Chip Enable (Flash)

CE1#s

Chip Enable 1 (pSRAM/SRAM)

CE2s

Chip Enable 2 (pSRAM/SRAM)

OE#

Output Enable (Common)

WE#

Write Enable (Common)

RY/BY#

Ready/Busy Output (Flash 1)

UB#

Upper Byte Control (pSRAM/SRAM)

LB#

Lower Byte Control (pSRAM/SRAM)

RESET#

Hardware Reset Pin, Active Low (Flash)

WP#/ACC

Hardware Write Protect/Acceleration Pin (Flash)

Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage

supply tolerances)

pSRAM/SRAM Power Supply

Device Ground (Common)

NC

Pin Not Connected Internally