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RT9645GQV Datasheet(PDF) 9 Page - Richtek Technology Corporation |
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RT9645GQV Datasheet(HTML) 9 Page - Richtek Technology Corporation |
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9 / 13 page  RT9645 Preliminary 9 DS9645-00 August 2007 www.richtek.com Overview The RT9645 integrates two synchronous buck PWM controllers, two LDO controllers, and a dual power switching controller. It is primarily designed for computer applications powered from an ATX power supply. A 300kHz Synchronous Buck PWM controller with a precision 0.8V reference provides the proper Core voltage to the system main memory. A second 300kHz PWM Buck controller which requires an external MOSFET driver, provides the GMCH core voltage. One LDO controller regulates for FSB_VTT termination and other one is for the 3VSB power regulation. RT9645 also provides a dual power control 5VDL for S0 and S3 system power. Table 1 State VCC_D RV SB5V_DR V 5VDL S5 L H Off S3 L L On S0 H H On State FSB_VTT 3VSB VDDQ S5 Off On Off S3 Off On On S0 On On On ACPI State Transitions ACPI compliance is realized through the S3 and S5 sleep signals. Figure 3 shows how the RT9645 regulators are working during all state transitions. S5 to S0 Transition After AC power is plugged, the RT9645 stays in S5 state until the power button is pushed on. The S3 and S5 signals transit to HIGH and the +12V rail starts to ramp up. The RT9645 POR is executed as soon as PVIN voltage exceeds the threshold. In Intel mode, after an internal time delay TSS the VDDQ PWM will enable soft-start sequence and VCC_DRV will change to high. In AMD mode, VDDQ PWM is enabled after VDDQ_EN goes high. FSB_VTT soft-start will follow VDDQ soft-start with a time delay TSS in Intel mode, but in AMD mode FSB_VTT soft-start is triggered by VTT_EN becoming high. After VDDQ rail and the FSB_VTT soft- start completes, all RT9645 regulators work in normal operation. Refer to Figure 3 and Figure 4 for the detailed timing diagrams. OCSET OCSET DS(ON) 40 A R I R μ× = Application Information S0 to S3 Transition When S3 goes LOW but S5 still HIGH ,the RT9645 will disable FSB_VTT regulators. SB5V_DRV and VCC_DRV will go low to continually power on 5VDL rail. The memory power VDDQ is also maintained. S3 to S0 Transition When S3 transits from LOW to HIGH with S5 keeps HIGH and after the PVIN exceeds its POR threshold, in Intel mode the RT9645 will wait a time delay TSS and then soft- starts FSB_VTT LDO. In AMD mode, FSB_VTT will soft- start after VTT_EN goes high. S0 to S5 Transition When the system transits from active state to shutdown (S0 to S5) state, the RT9645 keeps powering 3VSB and turn off the other power regulators. Fault Protection The RT9645 monitors the VDDQ ,PWM2 and 3VSB regulator for under voltage and over-current protection. The FSB_VTT LDO regulator is monitored for under voltage protection. If RT9645 detects thermal Shutdown, over current (or Under Voltage) of 3VSB, the RT9645 will immediately shutdown all regulators and jump to first system state to redo power sequence. When VDDQ issues Under Voltage or Over Current or FSB_VTT issues Under Voltage, the RT9645 will immediately enters into S5 sleep state.This can only be cleared by toggling the S5 signal. VDDQ and PWM2 Over Current Protection The RT9645 senses the current flowing through low side MOSFET for over current protection (OCP). A 40 μAcurrent source flows through the external resistor ROCSET to PHASE pin causes 40 μA x ROCSET voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET VDS) is lower than Rocset voltage drop when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET RDS(ON) as : |
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