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RT9285CGQW Datasheet(PDF) 9 Page - Richtek Technology Corporation |
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RT9285CGQW Datasheet(HTML) 9 Page - Richtek Technology Corporation |
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9 / 13 page  RT9285C Preliminary 9 DS9285C-00 August 2007 www.richtek.com As GPIO = 1.8V, VOUT = RA x {(0.25/RB) + (0.25-1.8)/ RGPIO)} + 0.25 (4) For Efficiency Consideration : Set RA = 990k Ω, If 2 levels are 16V (GPIO = 0V) and 14V (GPIO = 1.8V) Get RB = 16k Ω, RGPIO = 890kΩ Table 2. Suggested Resistance for Output Voltage Control Conditions RA (k Ω) RB (k Ω) RGPIO (k Ω) Case A : Normal Voltage = 16V (GPIO = 0V) Dimming Voltage = 12V (GPIO = 1.8V) 1100 18 495 Case B : Normal Voltage = 16V (GPIO = 0V) Dimming Voltage = 12V (GPIO = 2.8V) 1200 19.5 840 Considering the output voltage deviation from the GPIO voltage tolerance, as GPIO voltage vibrated by 0 ± 50mV and 1.8(2.8) ±5% ,the output voltage could be kept within ±2.5%. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) - TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125 °C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9285C, where TJ (MAX) is the maximum junction temperature of the die (125 °C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For XDFN/WDFN 2x2 packages, the thermal resistance θJA is 165蚓 /W on the standard JEDEC 51-3 single layer thermal test board. The maximum power dissipation at TA= 25 °C can be calculated by following formula: PD(MAX) = (125 °C − 25°C) / (165°C/W) = 0.606 W forWDFN/ XDFN 2x2 packages PD(MAX) = (125 °C − 25°C) / (255°C/W) = 0.392 W for TSOT- 23-6 packages The maximum power dissipation depends on operating ambient temperature for fixed TJ (MAX) and thermal resistance θJA. For RT9285C packages, the Figure 6 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Figure 6. Derating Curves for RT9285C Packages 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 25 50 75 100 125 Ambient Temperature ( °C) TSOT-23-6 XDFN/WDFN-8L 2x2 Layout guide } A full GND plane without gap break. } Traces in bold need to be routed first and should be kept as short as possible. } VDD to GND noise bypass : Short and wide connection for the 1uF MLCC capacitor between Pin 6 and Pin 2. } LX node copper area should be minimized for reducing EMI. (*1) } The input capacitor C1 should be placed as closed as possible to Pin 6. (*2) |
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