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RT9173CPSP Datasheet(PDF) 11 Page - Richtek Technology Corporation |
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RT9173CPSP Datasheet(HTML) 11 Page - Richtek Technology Corporation |
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11 / 13 page  RT9173C 11 DS9173C-12 September 2007 www.richtek.com Figure 5 RDS(ON) vs. Temperature 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 Temperature ( °C) VCNTL = 5V Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the RT9173C. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between RT9173C and the preceding power converter. Thermal Consideration RT9173C regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed maximum operation junction temperature 125 °C. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) -TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125 °C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance ( θJA is layout dependent) for SOP-8 package (Exposed Pad) is 75 °C/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25 °C can be calculated by following formula: PD(MAX) = (125 °C - 25°C) / 75°C/W = 1.33W Figure 6 show the package sectional drawing of SOP-8 (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 7, the thermal resistance equivalent circuit of SOP-8 (Exposed Pad). The path 2 is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path 2. Ambient Molding Compound Gold Line Lead Frame Die Pad Case (Exposed Pad) Figure 6. SOP-8 (Exposed Pad) Package Sectional Drawing Figure 7. Thermal Resistance Equivalent Circuit Junction R DIE R DIE-ATTACH RDIE-PAD R GOLD-LINE R LEAD FRAME Case (Exposed Pad) R PCB R PCB Ambient R MOLDING-COMPOUND path 1 path 2 path 3 The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP-8 package. About PCB layout, the Figure 8 show the relation between thermal resistance θJA and copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA = 25 °C.We have to consider the copper couldn't stretch |
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