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EN25B05-50VCP Datasheet(PDF) 8 Page - Eon Silicon Solution Inc. |
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EN25B05-50VCP Datasheet(HTML) 8 Page - Eon Silicon Solution Inc. |
8 / 30 page This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 EN25B05 Rev. B, Issue Date: 2006/12/26 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 4. Instruction Set Instruction Name Byte 1 Code Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes Write Enable 06h Write Disable 04h Read Status Register 05h (S7-S0)(1) continuous (2) Write Status Register 01h S7-S0 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) continuous Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) (Next Byte) continuous Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 (Next byte) continuous Sector Erase D8h A23-A16 A15-A8 A7-A0 Bulk Erase C7h Deep Power-down B9h Release from Deep Power-down, and read Device ID dummy dummy dummy (ID7-ID0) (4) Release from Deep Power-down ABh Manufacturer/ Device ID 90h dummy dummy 00h (M7-M0) (ID7-ID0) (5) Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0) Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until CS# terminate the instruction. 3. All sectors may use any address within the sector. 4. The Device ID will repeat continuously until CS# terminate the instruction. 5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction. |
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