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CCD595 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. CCD595
Description  9216 x 9216 Pixel Image Area Full Frame CCD Image Sensor
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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CCD595 Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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PRELIMINARY DATA SHEET
Fairchild Imaging, Inc., 1801 McCarthy Blvd, Milpitas 95035, (800) 325-6975, (408) 433-2500
FEATURES
9216 x 9216 Full Frame CCD Array
8.75
µµµµm x 8.75 µµµµm Pixels
80.64mm x 80.64mm Image Area
100% Fill Factor
Non Multi-Pinned Phase (MPP) Operation
8 Outputs (4 on each side)
Readout Noise Less Than 30 e
- at 100MHz (25MHz x 4)
GENERAL DESCRIPTION
The CCD595 is a 9216 x 9216 active element solid state Charge
Coupled Device (CCD) Full Frame sensor. The CCD is intended for
advanced scientific, space, and aerial reconnaissance applications. The
CCD595 is organized as an array of 9216 horizontal by 9216 vertical
imaging elements. The pixel pitch is 8.75
µm with a 100% fill factor.
Three-phase clocking is employed in the imaging area with two-phase
clocking in the serial readout registers. Image readout is performed via 4
serial registers containing 19 isolation rows between imaging and
readout sections. The imaging array can be clocked unidirectional (4-
output configuration) or bi-directional (8-output configuration). The
imaging area segments are split in mid-array for the latter configuration.
To maximize the exposure/readout cycle rate, concurrent array and
serial register clocking is utilized. Fast transfer clocking between the
array and serial registers is accomplished with strapped transfer gates
that load each line in less than 5 microseconds.
The output circuit architecture features eight (four active, eight optional)
three stage source follower readouts. The nominal read noise of the
output amplifiers is less than 25 electrons at 25MHz. The combined data
rates for 4 and 8 output configurations are 100MHz and 200MHz
respectively. Internal temperature and humidity sensors are also located
near the FPA for external monitoring.
The top of the package has an optical window over the CCD active
area. The CCD595 is mounted in an environmentally sealed
enclosure containing the CCD array with thermoelectric coolers for
controlling the operating temperature of the array.
Pinouts are provided on three sides for electrical connections (4-
output configuration). The package base serves as the heat sink
interface for thermal management. A mounting flange at the
package rim is used as a Z-axis reference datum for the
planarization of the CCD focal plane with external optics.
DC OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
RANGE
MIN
NOM
MAX
UNIT
REMARKS
VDD
DC Supply Voltage
18.0
20.0
23.0
V
VRD
Reset Drain Voltage
14.0
17.0
20.0
V
VOG
Output Gate Voltage
0.0
1.0
5.0
V
VSS
Substrate Ground
0.0
V
Vodc
Output DC Level
VRD-5
VRD-4
V
Z
Suggested Load Resistor
0.8
1.0
1.8
K ohms
TYPICAL CLOCK VOLTAGES
SYMBOL
PARAMETER
HIGH
LOW
UNIT
REMARKS
V
φH(1,2),
φSG
Horizontal Transport Clock Voh Max-Min
+7.5
+10
-7.5
V
V
+4.5, -0.5 Typical
V
φV (1,2,3)
Vertical Transport Clocks
+8.0
-10.0
V
+5, -10 V Typical
V
φR
Reset Gate Clock
+15.0
0.0
V
+2.0 +8.0 V Typical
V
φVTG (2,3)
Array Transfer Gate Clock
+8.0
-10.0
V
+5, -10 Typical
C
φV(1,2,3)
Vertical Array Gates
A1
Cap. (per
φV)
A2
A3
47
86
109
30
38
31
nF
Min @ +10V
Max @ -10V
C
φVTG2,3
Array Transfer Gate
TG2
Cap. (per pin)
TG3
200
200
150
150
pF
Min @ +10V
Max @ -10V
C
φH (1,2)
Horizontal Transfer Gate
S1
Cap. (per
φ H)
S2
65
76
pF
Min @ +10V
Max @ -10V
C
φH
Horizontal Transfer Gate
S1
Cap. (per pin)
S2
65
76
pF
Min @ +10V
Max @ -10V
Note 1:
φH = 400 pF, φV = 60,000 pF. All clock rise and fall times should be > 10 ns.
CCD595
9216 x 9216 Pixel Image Area
Full Frame CCD Image Sensor


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