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RP144D Datasheet(PDF) 7 Page - Synaptics Incorporated.

Part # RP144D
Description  Low Voltage V.90/ K56flex / V.34/ v.32bis Modem Data Pumps for Desktop Applications
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Manufacturer  CONEXANT [Synaptics Incorporated.]
Direct Link  https://www.synaptics.com/
Logo CONEXANT - Synaptics Incorporated.

RP144D Datasheet(HTML) 7 Page - Synaptics Incorporated.

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When the transmitter's converter is operating at the basic
signaling rate, no more than one stop bit will be deleted
per 8 consecutive characters. When operating at the
extended rate, no more than one stop bit will be deleted
per 4 consecutive characters. Break handling is
performed as described in V.14.
Asynchronous characters are accepted on the TXD serial
input and are issued on the RXD serial output.
V.54 Inter-DCE Signaling
The MDP supports V.54 inter-DCE signaling procedures
in synchronous and asynchronous configurations.
Transmission and detection of the preparatory,
acknowledgment, and termination phases as defined in
V.54 are provided. Three control bits in the transmitter
allow the host to send the appropriate bit patterns (V54T,
V54A, and V54P bits). Three control bits in the receiver
are used to enable one of three bit pattern detectors
(V54TE, V54AE, and V54PE bits). A status bit indicates
when the selected pattern detector has found the
corresponding bit pattern (V54DT bit).
V.13 Remote RTS Signaling
The MDP supports V.13 remote RTS signaling.
Transmission and detection of signaling bit patterns in
response to a change of state in the RTS bit or the ~RTS
input signal are provided. The RRTSE bit enables V.13
signaling. The RTSDE bit enables detection of V.13
patterns. The RTSDT status bit indicates the state of the
remote RTS signal. This feature may be used to
clamp/unclamp the local ~RLSD and RXD signals in
response to a change in the remote RTS signal in order to
simulate controlled carrier operation in a constant carrier
environment. The MDP automatically clamps and
unclamps ~RLSD.
Dialing and Answering
The host can dial and answer using supported
DTMF/pulse dialing and tone detection functions. The
major parameters are host programmable.
Supervisory Tone Detection
Three parallel tone detectors (A, B, and C) are provided
for supervisory tone detection. The signal path to these
detectors is separate from the main received signal path.
Each tone detector consists of two cascaded second
order IIR biquad filters. The coefficients are host
programmable. Each fourth order filter is followed by a
level detector which has host programmable turn-on and
turn-off thresholds allowing hysteresis. Tone detector C is
preceded by a prefilter and squarer. This circuit is useful
for detecting a tone with frequency equal to the difference
between two tones that may be simultaneously present on
the line. The squarer may be disabled by the SQDIS bit
causing tone detector C to be an eighth order filter. The
tone detectors are disabled in data mode.
The tone detection sample rate is 9600 Hz in V.8 and
V.34 modes and is 7200 Hz in non-V.34 modes. The
default call progress filter coefficients are based on a
7200 Hz sampling rate and apply to non-V.34 modes only.
The maximum detection bandwidth is equal to one-half
the sample rate.
The default bandwidths and thresholds of the tone
detectors are:
Tone Detector
Bandwidth
Turn-On
Threshold
Turn-Off
Threshold
A
245 – 650 Hz
–25 dBm
–31 dBm
B
360 – 440 Hz
–25 dBm
–31 dBm
C Prefilter
0 – 500 Hz
N/A
N/A
C
50 – 110 Hz
*
*
* Tone Detector C will detect a difference tone within its
bandwidth when the two tones present are in the range –1 dBm
to –26 dBm.
511 Pattern Generation/Detection
In synchronous mode, a 511 pattern can be generated
and detected (control bit S511). Use of this bit pattern
during self-test eliminates the need for external test
equipment.
In-Band Secondary Channel
A full-duplex in-band secondary channel is provided in
V.34 (all speeds) and V.32 bis/V.32 (7200 bps and above)
modes. Control bit SECEN enables and disables the
secondary channel operation. The secondary channel
operates in parallel data mode with independent transmit
and receive interrupts and data buffers. The main channel
may operate in parallel or serial mode.
In V.34 modes, the secondary channel rate is 200 bps.
In V.32 bis/V.32 modes, the secondary channel rate is
150 bps. This rate is also host programmable in V.32
bis/V.32 modes.
Transmit and Receive FIFO Data Buffers
Two (16+128)-byte first-in first-out (FIFO) data buffers
allow the DTE/host to rapidly output up to 144 bytes of
transmit data and input up to 144 bytes of accumulated
received data. The receiver FIFO is always enabled. The
transmitter FIFO is enabled by the FIFOEN control bit.
TXHF and RXHF bits operate off the lower 16 bits and
indicate the corresponding FIFO buffer half full (8 or more
bytes loaded) status. TXFNF and RXFNE bits indicate the
TXFIFO buffer not full and RXFIFO buffer not empty
status, respectively. An interrupt mask register allows an
interrupt request to be generated whenever the TXFNF,
RXFNE, RXHF, or TXHF status bit changes state. The
128-byte FIFO extensions are enabled by default and can
be disabled by clearing a bit in RAM.
DMA Support Interrupt Request Lines
DMA support is available in synchronous, asynchronous,
and HDLC parallel data modes. Control bit DMAE enables
and disables DMA support. When DMA support is
enabled, the MDP ~RI and ~DSR lines are assigned to
Transmitter Request (TXRQ) and Receiver Request
(RXRQ) hardware output interrupt request lines,
respectively. The TXRQ and RXRQ signals follow the
assertion of the TDBE and RDBF interrupt bits thus
allowing the DTE/host to respond immediately to the


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