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VIPER50ASP-E Datasheet(PDF) 12 Page - STMicroelectronics

Part No. VIPER50ASP-E
Description  SMPS PRIMARY I.C.
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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VIPER50ASP-E Datasheet(HTML) 12 Page - STMicroelectronics

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5 Operation Description
VIPer50A-E/ASP-E
12/31
As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase
above the 13V regulation level, forcing the output voltage of the transconductance amplifier to
low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power
switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as
VDD gets back to the regulation level and the VCOMPth threshold is reached, the device
operates again. The above cycle repeats indefinitely, providing a burst mode of which the
effective duty cycle is much lower than the minimum one when in normal operation. The
equivalent switching frequency is also lower than the normal one, leading to a reduced
consumption on the input main supply lines. This mode of operation allows the VIPer50A-E/
ASP-E to meet the new German "Blue Angel" Norm with less than 1W total power consumption
for the system when working in stand-by mode. The output voltage remains regulated around
the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of
this ripple is low, because of the output capacitors and low output current drawn in such
conditions.The normal operation resumes automatically when the power gets back to higher
levels than PSTBY.
5.3
High Voltage Start-up Current Source
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits which are
placed into a standby mode with reduced consumption and also provided to the external
capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage
threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The
start-up current generator is switched off, and the converter should normally provide the
needed current on the VDD pin through the auxiliary winding of the transformer, as shown on
(see Figure 11).
In case there are abnormal conditions where the auxiliary winding is unable to provide the low
voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the
external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the
device goes back to the inactive state where the internal circuits are in standby mode and the
start-up current source is activated. The converter enters a endless start-up cycle, with a start-
up duty cycle defined by the ratio of charging current towards discharging when the device tries
to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while
the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.
This low value start-up duty cycle prevents the application of stress to the output rectifiers as
well as the transformer when a short circuit occurs.
The external capacitor CVDD on the VDD pin must be sized according to the time needed by the
converter to start up, when the device starts switching. This time tSS depends on many
parameters, among which transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin. The following formula can be used for
defining the minimum capacitor needed:
where:
IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
C
VD D
I
DD
t
SS
V
DD hys t
--------------------
>


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