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VIPER50ASP-E Datasheet(PDF) 11 Page - STMicroelectronics

Part No. VIPER50ASP-E
Description  SMPS PRIMARY I.C.
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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VIPER50ASP-E Datasheet(HTML) 11 Page - STMicroelectronics

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VIPer50A-E/ASP-E
5 Operation Description
11/31
5
Operation Description
5.1
Current Mode Topology:
The current mode control method, like the one integrated in the VIPer50A-E/ASP-E, uses two
control loops - an inner current control loop and an outer loop for voltage control. When the
Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is
monitored with a SenseFET technique and converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified output voltage error) the power switch is
switched off. Thus, the outer voltage control loop defines the level at which the inner loop
regulates peak current through the power switch and the primary winding of the transformer.
Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.
Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
power supply on VDD is no longer correct. For specific applications the maximum peak current
internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.
5.2
Stand-by Mode
Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power PSTBY given by :
Where:
LP is the primary inductance of the transformer. FSW is the normal switching frequency.
ISTBY is the minimum controllable current, corresponding to the minimum on time that the
device is able to provide in normal operation. This current can be computed as :
tb + td is the sum of the blanking time and of the propagation time of the internal current sense
and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage.
P
STB Y
1
2
---L
PI
2
ST BY
F
SW
=
I
STB Y
t
b
t
d
+
()V
IN
L
p
-----------------------------
=


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