SN65LBC176A, SN75LBC176A

DIFFERENTIAL BUS TRANSCEIVERS

SLLS376C− MAY 2000 − REVISED DECEMBER 2000

5

POST OFFICE BOX 655303

receiver electrical characteristics over recommended operating conditions (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIT +

Positive-going input threshold

voltage

IO = −8 mA

0.2

V

VIT −

Negative-going input threshold

voltage

IO = 8 mA

− 0.2

V

Vhys

Hysteresis voltage (VIT + − VIT −)

IO = 8 mA

50

mV

VIK

Enable-input clamp voltage

II = − 18 mA

− 1.5

− 0.8

V

VOH

High-level output voltage

VID = 200 mV, IOH = − 8 mA,

See Figure 6

4

4.9

V

VOL

Low-level output voltage

VID = 200 mV, IOL = 8 mA,

See Figure 6

0.1

0.8

V

SN65LBC176AQ

−10

10

IOZ

High-impedance-state output current

VO = 0 to VCC

SN65LBC176A,

SN75LBC176A

−1

1

µA

VIH = 12 V,

VCC = 5 V

0.4

1

II

Bus input current

VIH = 12 V,

VCC = 0

Other input at 0 V

0.5

1

mA

II

Bus input current

VIH = − 7 V,

VCC = 5 V

Other input at 0 V

−0.8

− 0.4

mA

VIH = − 7 V,

VCC = 0

−0.8

− 0.3

IIH

High-level enable-input current

VIH = 2 V

− 100

µA

IIL

Low-level enable-input current

VIL = 0.8 V

− 100

µA

VI = 0 or VCC,

Receiver enabled and driver disabled

4

7

ICC

Supply current

VI = 0 or VCC,

No load

Receiver disabled and driver disabled

0.4

0.7

mA

ICC

Supply current

No load

Receiver enabled and driver enabled

8.5

15

mA

† All typical values are at VCC = 5 V, TA = 25°C.

receiver switching characteristics over recommended operating conditions (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

SN65LBC176AQ

SN65LBC176A

SN75LBC176A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

tPLH

Propagation delay time, output

↑

VID = − 1.5 V to 1.5 V,

7

30

7

13

20

ns

tPHL

Propagation delay time, output

↓

VID = − 1.5 V to 1.5 V,

See Figure 7

7

30

7

13

20

ns

tsk(p)

Pulse skew ( | tPHL − tPLH |)

See Figure 7

6

0.5

1.5

ns

tr

Rise time, output

See Figure 7

5

2.1

3.3

ns

tf

Fall time, output

See Figure 7

5

2.1

3.3

ns

tPZH

Output enable time to high level

50

30

45

ns

tPZL

Output enable time to low level

CL = 10 pF,

50

30

45

ns

tPHZ

Output disable time from high level

CL = 10 pF,

See Figure 8

60

20

40

ns

tPLZ

Output disable time from low level

See Figure 8

40

20

40

ns

† All typical values are at VCC = 5 V, TA = 25°C.