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HYI18T1G800BF-3.7 Datasheet(PDF) 9 Page - Qimonda AG |
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HYI18T1G800BF-3.7 Datasheet(HTML) 9 Page - Qimonda AG |
9 / 74 page Internet Data Sheet Rev. 1.3, 2007-07 9 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM 2 Configuration This chapter contains the chip configuration and addressing. 2.1 Chip Configuration for PG-TFBGA-68 The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball# and Buffer Type columns are explained in Table 8 and Table 9 respectively. The ball numbering for the FBGA package is depicted in figures. TABLE 7 Chip Configuration of DDR2 SDRAM Ball# Name Ball Type Buffer Type Function Clock Signals ×4×8 Organizations J8 CK I SSTL Clock Signal CK, CK K8 CK I SSTL K2 CKE I SSTL Clock Enable Control Signals ×4×8 Organizations K7 RAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) L7 CAS I SSTL K3 WE I SSTL L8 CS I SSTL Chip Select Address Signals ×4×8 Organizations L2 BA0 I SSTL Bank Address Bus 1:0 L3 BA1 I SSTL L1 BA2 I SSTL Bank Address Bus 2 Note: 1 Gbit components and higher |
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