TMS28F008Axy,TMS28F800Axy

1048576 BY 8-BIT/524 288 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998

36

POST OFFICE BOX 1443

timing requirements for TMS28F008AVy or ’ALy and TMS28F800AVy or ’ALy (commercial and

extended temperature ranges) (continued)

write/erase operations — CE-controlled writes

ALT.

SYMBOL

’28F008AVy 100

’28F800AVy 100

’28F008ALy100

’28F800ALy100

’28F008AVy80

’28F800AVy80

’28F008ALy80

’28F800ALy80

UNIT

MIN

MAX

MIN

MAX

tc( E )

Cycle time, write

tAVAV

100

120

ns

tc(E)OP

Cycle time, duration of programming operation

tEHQV1

6

6

µs

tc(E)ERB

Cycle time, erase operation (boot block)

tEHQV2

0.3

0.3

s

tc(E)ERP

Cycle time, erase operation (parameter block)

tEHQV3

0.3

0.3

s

tc(E)ERM

Cycle time, erase operation (main block)

tEHQV4

0.6

0.6

s

td(RPR)

Delay time, boot-block relock

tPHBR

200

200

ns

th(A)

Hold time, A0 – A18 (see Note 14)

tEHAX

0

0

ns

th(D)

Hold time, DQ valid

tEHDX

0

0

ns

th( W )

Hold time, WE

tEHWH

0

0

ns

th (VPP)

Hold time, VPP from valid status-register bit

tQVVL

0

0

ns

th(RP)

Hold time, RP at VHH from valid status-register bit

tQVPH

0

0

ns

th(WP)

Hold time, WP from valid status-register bit

tWHPL

0

0

ns

tsu(WP)

Setup time, WP before write operation

tELPH

90

100

ns

tsu(A)

Setup time, A0 – A18 (see Note 14)

tAVEH

90

100

ns

tsu(D)

Setup time, DQ

tDVEH

90

100

ns

tsu( W )

Setup time, WE before write operation

tWLEL

0

0

ns

tsu(RP)

Setup time, RP at VHH to CE going high

tPHHEH

200

100

ns

tsu( VPP)2

Setup time, VPP to CE going high

tVPEH

200

100

ns

tw(E)

Pulse duration, CE low

tELEH

90

100

ns

tw( EH)

Pulse duration, CE high

tEHEL

20

30

ns

trec(RPHE) Recovery time, RP high to CE going low

tPHEL

1.5

1.5

µs

NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB

address.