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HYS72T64001HR Datasheet(PDF) 33 Page - Qimonda AG |
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HYS72T64001HR Datasheet(HTML) 33 Page - Qimonda AG |
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33 / 67 page  Internet Data Sheet Rev. 1.21, 2007-03 33 09152006-J5FK-C565 HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3.4 I DD Specifications and Conditions This chapter describes the I DD Specifications and Conditions. TABLE 22 I DD Measurement Conditions Parameter Symbol Note1)2) 3)4)5)6) Operating Current 0 One bank Active - Precharge; t CK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. I DD0 Operating Current 1 One bank Active - Read - Precharge; I OUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, t RCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. I DD1 Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; t CK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING I DD2N Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. I DD2P Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; t CK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. I DD2Q Active Power-Down Current All banks open; t CK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); I DD3P(0) Active Power-Down Current All banks open; t CK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); I DD3P(1) Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; t RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; I OUT = 0 mA. I DD3N Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; t RAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; I OUT = 0 mA. I DD4R Operating Current Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; t RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; I DD4W Burst Refresh Current t CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. I DD5B Distributed Refresh Current t CK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. I DD5D |
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