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HYS72D64301 Datasheet(PDF) 6 Page - Qimonda AG |
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HYS72D64301 Datasheet(HTML) 6 Page - Qimonda AG |
6 / 51 page Internet Data Sheet Rev. 1.42, 2007-01 6 03292006-7CZA-YS85 HYS72D[64/128/256]xxx[G/H]BR–[5/6/7]–B Registered DDR SDRAM Module 2 Pin Configuration The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Figure 1. TABLE 4 Pin Configuration of RDIMM Pin# Name Pin Type Buffer Type Function Clock Signals 137 CK0 I SSTL Clock Signal 138 CK0 I SSTL Complement Clock 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 Note: 2-rank module NC NC SSTL Note: 1-rank module Control Signals 157 S0 I SSTL Chip Select of Rank 0 158 S1 I SSTL Chip Select of Rank 1 Note: 2-ranks module NC NC — Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe 63 WE I SSTL Write Enable 10 RESET ILV- CMOS Register Reset Address Signals 59 BA0 I SSTL Bank Address Bus 1:0 52 BA1 I SSTL 48 A0 I SSTL Address Bus 11:0 43 A1 I SSTL 41 A2 I SSTL 130 A3 I SSTL 37 A4 I SSTL 32 A5 I SSTL |
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