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ML145554EP Datasheet(PDF) 3 Page - LANSDALE Semiconductor Inc. |
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ML145554EP Datasheet(HTML) 3 Page - LANSDALE Semiconductor Inc. |
3 / 18 page LANSDALE Semiconductor, Inc. ML145554, ML145557, ML145564, ML145567 DEVICE DESCRIPTION A codec–filter is used for digitizing and reconstructing the- human voice. These devices were developed primarily for the telephone network to facilitate voice switching and transmis- sion. Once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec is an acronym from “COder” (for the A/D used to digi- tize voice) and “DECoder” (for the D/A used for reconstruct- ing voice). A codec is a single device that does both the A/D and D/A conversions. To digitize intelligible voice requires a signal–to–distortion ratio of about 30 dB over a dynamic range of about 40 dB. This can be accomplished with a linear 13–bit A/D and D/A, but will far exceed the required signal–to–distortion ratio at amplitudes greater than 40 dB below the peak amplitude. This excess performance is at the expense of data per sample. Methods of data reduction are implemented by compressing the 13–bit linear scheme to companded 8–bit schemes. There are two companding schemes used: Mu–255 Law specifically in North America, and A–Law specifically in Europe. These companding schemes are accepted world wide. These com- panding schemes follow a segmented or “piecewise–linear” curve formatted as sign bit, three chord bits, and four step bits. For a given chord, all sixteen of the steps have the same volt- age weighting. As the voltage of the analog input increases, the four step bits increment and carry to the three chord bits which increment. When the chord bits increment, the step bits double their voltage weighting. This results in an effective resolution of six bits (sign + chord + four step bits) across a 42 dB dynamic range (seven chords above zero, by 6 dB per chord). Tables 3 and 4 show the linear quantization levels to PCM words for the two companding schemes. In a sampling environment, Nyquist theory says that to prop- erly sample a continuous signal, it must be sampled at a fre- quency higher than twice the signal’s highest frequency com- ponent. Voice contains spectral energy above 3 kHz, but its absence is not detrimental to intelligibility. To reduce the digi- tal data rate, which is proportional to the sampling rate, a sam- ple rate of 8 kHz was adopted, consistent with a bandwidth of 3 kHz. This sampling requires a low–pass filter to limit the high frequency energy above 3 kHz from distorting the in–band signal. The telephone line is also subject to 50/60 Hz power line coupling, which must be attenuated from the signal by a high–pass filter before the A/D converter. The D/A process reconstructs a staircase version of the desired in–band signal, which has spectral images of the in–band signal modulated about the sample frequency and its harmonics. These spectral images, called aliasing components, need to be attenuated to obtain the desired signal. The low–pass filter used to attenuate these aliasing components is typically called a reconstruction or smoothing filter. The ML145554/57/64/67 PCM Codec–Filters have the codec, both presampling and reconstruction filters, and a pre- cision voltage reference on–chip, and require no external com- ponents. PIN DESCRIPTION DIGITAL FSR Receive Frame Sync This is an 8 kHz enable that must be synchronous with BCLKR. Following a rising FSR edge, a serial PCM word at DR is clocked by BCLKR into the receive data register. FSR also initiates a decode on the previous PCM word. In the ab- sence of FSX, the length of the FSR pulse is used to deter- mine whether the I/O conforms to the Short Frame Sync or Long Frame Sync convention. DR Receive Digital Data Input BCLKR/CLKSEL Receive Data Clock and Master Clock Frequency Selector If this input is a clock, it must be between 128 kHz and 4.096 MHz, and synchronous with FSR. In synchronous appli- cations this pin may be held at a constant level; then BCLKX is used as the data clock for both the transmit and receive sides, and this pin selects the assumed frequency of the master clock (see Table 1 in Functional Description). MCLKR/PDN Receive Master Clock and Power–Down Control Because of the shared DAC architecture used on these devices, only one master clock is needed. Whenever FSX is clocking, MCLKX is used to derive all internal clocks, and the MCLKR/PDN pin merely serves as a power–down control. If MCLKR/PDN pin is held low or is clocked (and at least one of the frame syncs is present), the part is powered up. If this pin is held high, the part is powered down. If FSX is absent but FSR is still clocking, the device goes into receive half–channel mode, and MCLKR (if clocking) generates the internal clocks. MCLKX Transmit Master Clock This clock is used to derive the internal sequencing clocks; it must be 1.536 MHz, 1.544 MHz, or 2.048 MHz. BCLKX Transmit Data Clock BCLKX may be any frequency between 128 kHz and 4.096 MHz, but it should be synchronous with MCLKX. DX Transmit Digital Data Output This output is controlled by FSX and BCLKX to output the PCM data word; otherwise this pin is in a high–impedance state. FSX Transmit Frame Sync This is an 8 kHz enable that must be synchronous with BCLKX. A rising FSX edge initiates the transmission of a www.lansdale.com Page 3 of 18 Issue A |
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