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EVAL-AD7470 Datasheet(PDF) 4 Page - Analog Devices

Part No. EVAL-AD7470
Description  Evaluation Board for 10-/12-Bit High Speed, Low Power ADCs
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EVAL-AD7470 Datasheet(HTML) 4 Page - Analog Devices

 
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EVAL-AD7470/AD7472
Rev. C | Page 4 of 20
Link No.
Function
LK4
This link option selects the source of the CONVST input.
In Position A, the CONVST input is provided by the EVAL-CONTROL BOARD2.
In Position B, the CONVST input is provided via the external socket, SK2.
LK5
This link option selects the source of the RD input.
In Position A, the RD input is provided by the EVAL-CONTROL BRD2.
In Position B, the RD input is tied to GND.
LK6
This link option selects the source of the CS input.
In Position A, the CS input is provided by the EVAL-CONTROL BRD2.
In Position B, the CS input is tied to GND.
LK7
This link option sets the voltage applied to the VDRIVE pin on the AD7470/AD7472.
In Position A, VDRIVE is connected directly to the DVDD pin.
In Position B, an external voltage must be applied to the VDRIVE pin via J3.
LK8
This link selects the source of the VDD supply.
In Position A, VDD must be supplied from an external source via J2.
In Position B, VDD is supplied from the EVAL-CONTROL BRD2.
LK9
This link selects the source of the VSS supply.
In Position A, VSS must be supplied from an external source via J2.
In Position B, VSS is supplied from the EVAL-CONTROL BRD2.
LK10
This link must be in Position A, if a bipolar AIN signal is being applied to the bipolar VIN socket, SK3.
This link must be in Position B, if a unipolar AIN signal is being applied to the unipolar VIN socket, SK5.
LK11
This link is used to provide a clock signal path to the burst mode circuit generator either from the on-board clock oscillator or
from an external clock source via SK1.
In Position A, the master clock signal is provided from the on-board crystal oscillator.
In Position B, the master clock signal must be provided from an external source via SK1.
SET-UP CONDITIONS
Before applying power and signals to the evaluation board, take care to ensure that all link positions are as per the required operating
mode. Table 2 shows the default positions of the links. All links are set for use with the EVAL-CONTROL BRD2.
Table 2. Initial Link and Switch Positions
Link No.
Position
Function
LK1
Inserted
Provides dc bias voltage to the analog bias-up circuit.
LK2
A
The digital logic circuitry is powered from the same voltage as the AD7470/AD7472.
LK3
A
The CLKIN signal is provided by the EVAL-CONTROL BRD2 via J1.
LK4
A
The CONVST signal is provided by the EVAL-CONTROL BRD2 via J1.
LK5
A
The RD signal is provided by the EVAL-CONTROL BRD2 via J1.
LK6
A
The CS signal is provided by the EVAL-CONTROL BRD2 via J1.
LK7
A
The AD7470/AD7472 VDRIVE pin is connected to the AD7470/AD7472 DVDD pin.
LK8
B
VDD is supplied by the EVAL-CONTROL BRD2 via J1.
LK9
B
VSS is supplied by the EVAL-CONTROL BRD2 via J1.
LK10
A
The AD7470/AD7472 VIN pin is connected to the output of the bias-up circuit.
LK11
A
Master clock for burst clock generator is provided from the on-board clock oscillator.


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