Internet Data Sheet

Rev. 1.42, 2007-09

6

03292006-TMTK-JFEU

HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)

256-MBit Synchronous DRAM

2

Configuration

This chapter contains the pin configuration table, the TSOP and FBGA package drawing, and the block diagrams for the

×4,

×8, ×16 organization of the SDRAM.

2.1

Pin Description

Listed below are the pin configurations sections for the various signals of the SDRAM.

TABLE 4

Pin Configuration of the SDRAM

Ball No. Name

Pin

Type

Buffer

Type

Function

Clock Signals

×4/×8/×16 Organization

38,2F

CLK

I

LVTTL

Clock Signal CK

37, 3F

CKE

I

LVTTL

Clock Enable

Control Signals

×4/×8/×16 Organization

18, 8F

RAS

ILVTTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)

17, 7F

CAS

ILVTTL

16, 9F

WE

ILVTTL

19, 9G

CS

ILVTTL

Chip Select

Address Signals

×4/×8/×16 Organization

20, 7G

BA0

I

LVTTL

Bank Address Signals 1:0

21, 8G

BA1

I

LVTTL

23, 7H

A0

I

LVTTL

Address Signal 12:0, Address Signal 10/Auto precharge

24, 8H

A1

I

LVTTL

25, 8J

A2

I

LVTTL

26, 7J

A3

I

LVTTL

29, 3J

A4

I

LVTTL

30, 2J

A5

I

LVTTL

31, 3H

A6

I

LVTTL

32, 2H

A7

I

LVTTL

33, 1H

A8

I

LVTTL

34, 3G

A9

I

LVTTL

22, 9H

A10

I

LVTTL

35, 2G

A11

I

LVTTL

36, 1G

A12

I

LVTTL