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HYB18TC256800BF Datasheet(PDF) 10 Page - Qimonda AG |
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HYB18TC256800BF Datasheet(HTML) 10 Page - Qimonda AG |
10 / 62 page Internet Data Sheet Rev. 1.3, 2007-05 10 07182006-DD60-22E6 HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM 2.2 Chip Configuration for PG-TFBGA-84 The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# columns are explained in Table 7 and Table 8 respectively. TABLE 9 Chip Configuration of DDR SDRAM Ball# Name Ball Type Buffer Type Function Clock Signals ×16 Organization J8 CK I SSTL Clock Signal CK, CK K8 CK I SSTL K2 CKE I SSTL Clock Enable Control Signals ×16 Organization K7 RAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) L7 CAS I SSTL K3 WE I SSTL L8 CS I SSTL Chip Select Address Signals ×16 Organization L2 BA0 I SSTL Bank Address Bus 1:0 L3 BA1 I SSTL M8 A0 I SSTL Address Signal 12:0,Address Signal 10/Autoprecharge M3 A1 I SSTL M7 A2 I SSTL N2 A3 I SSTL N8 A4 I SSTL N3 A5 I SSTL N7 A6 I SSTL P2 A7 I SSTL P8 A8 I SSTL P3 A9 I SSTL M2 A10 I SSTL AP I SSTL P7 A11 I SSTL R2 A12 I SSTL |
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