Data Sheet

Rev. 1.32, 2007-10

9

10122006-I6LJ-WV3H

HY[B/I]39S128[40/80/16][0/7]F[E/T](L)

128-MBit Synchronous DRAM

3

Functional Description

This chapter list all defined commands and their usage for this Synchronous DRAM family.

TABLE 5

Truth Table: Operation Command

Operation

Device State

CKE

1) V = Valid, x = Don’t Care, L = Low Level, H = High Level

2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.

CKE

n1)2)

DQM

1)2)

BA0

BA11)2)

AP=

A101)2)

Addr.

1)2)

CS1

)2)

RAS

1)2)

CAS1

)2)

WE

1)2)

Bank Active

3) This is the state of the banks designated by BA0, BA1 signals.

HX

X

V

V

V

L

L

H

H

Bank Precharge

Any

H

X

X

V

L

X

L

L

H

L

Precharge All

Any

H

X

X

X

H

X

L

L

H

L

Write

Active3)

HX

X

V

L

V

L

H

L

L

Write with Auto

precharge

Active3)

HX

X

V

H

V

L

H

L

L

Read

Active3)

HX

X

V

L

V

L

H

L

H

Read with Auto

precharge

Active3)

HX

X

V

H

V

L

H

L

H

Mode Register Set

Idle

H

X

X

V

V

V

L

L

L

L

No Operation

Any

H

X

X

X

X

X

L

H

H

H

Burst Stop

Active

H

X

X

X

X

X

L

H

H

L

Device Deselect

Any

H

X

X

X

X

X

H

X

X

X

Auto Refresh

Idle

H

H

X

X

X

X

L

L

L

H

Self Refresh Entry

Idle

H

L

X

X

X

X

L

L

L

H

Self Refresh Exit

Idle (Self Refr.)

L

H

X

X

X

X

H

X

X

X

LH

H

X

Power Down/

Clock Suspend Entry

Active or Idle

or Burst

HL

X

X

X

X

H

X

X

X

LH

H

H

Power Down/

Clock Suspend Exit

Active or Idle

or Burst

LH

X

X

X

X

H

X

X

X

LH

H

H

Data Write/

Output Enable

Active

H

X

L

X

X

X

X

X

X

X

Data Write/

Output Disable

Active

H

X

H

X

X

X

X

X

X

X