Preliminary Internet Data Sheet

Rev. 0.7, 2006-12

4

11292006-TAIE-H645

HYI25DC512[16/80]0CE

512-Mbit Double-Data-Rate SDRAM

1.2

Description

The 512-Mbit Double-Data-Rate SDRAM is a high-speed

CMOS,

dynamic

random-access

memory

containing

536,870,912 bits. It is internally configured as a quad-bank

DRAM.

The 512-Mbit Double-Data-Rate SDRAM uses a double-

data-rate architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n prefetch

architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access

for

the

512-Mbit Double-Data-Rate SDRAM

effectively consists of a single 2n-bit wide, one clock cycle

data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads and

by the memory controller during Writes. DQS is edge-aligned

with data for Reads and center-aligned with data for Writes.

The 512-Mbit Double-Data-Rate SDRAM operates from a

differential clock (CK and CK; the crossing of CK going HIGH

and CK going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write

command. The address bits registered coincident with the

Active command are used to select the bank and row to be

accessed. The address bits registered coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4 or 8 locations. An Auto Precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access. As

with standard SDRAMs, the pipelined, multibank architecture

of DDR SDRAMs allows for concurrent operation, thereby

providing high effective bandwidth by hiding row precharge

and activation time.

An auto refresh mode is provided along with a power-saving

power-down mode. All inputs are compatible with the Industry

Standard for SSTL_2. All outputs are SSTL_2, Class II

compatible.

Note: The functionality described and the timing

specifications included in this data sheet are for the

DLL Enabled mode of operation.

TABLE 2

Ordering Information for RoHS Compliant Products

Part Number

Org. CAS-RCD-RP

Latencies

Clock

(MHz)

CAS-RCD-RP

Latencies

Clock

(MHz)

Speed

Package

Note

HYI25DC512800CE–5

×8

3-3-3

200

2.5-3-3

166

DDR400B

PG-TSOPII-66

1)

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

HYI25DC512160CE–5

×16

HYI25DC512800CE–6

×8

2.5-3-3

166

2-3-3

133

DDR333

HYI25DC512160CE–6

×16