Internet Data Sheet

Rev. 1.42, 2007-09

3

03292006-TMTK-JFEU

HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)

256-MBit Synchronous DRAM

1Overview

This chapter lists all main features of the product family HYB39S256[400/800/160]F[E/T/F](L) and the ordering information.

1.1

Features

• Fully Synchronous to Positive Clock Edge

• 0 to 70

°C Standard Operating Temperature

• -40 to 85

°C Industrial Operating Temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2 & 3

• Programmable Wrap Sequence: Sequential or Interleave

• Programmable Burst Length: 1, 2, 4, 8 and full page

• Multiple Burst Read with Single Write Operation

• Automatic and Controlled Precharge Command

• Data Mask for Read / Write control (x4, x8)

• Data Mask for Byte Control (x16)

• Auto Refresh (CBR) and Self Refresh

• Power Down and Clock Suspend Mode

• 8192 refresh cycles / 64 ms (7.8

μs)

• Random Column Address every CLK (1-N Rule)

• Single 3.3 V ± 0.3 V Power Supply

• LVTTL Interface versions

• Packages:

– P(G)–TSOPII–54 (400mil width)

– PG–TFBGA–54

TABLE 1

Performance

Poduct Type Speed Code

–6

–7

Unit

Speed Grade

PC166–333

PC133–222

—

Max. Clock Frequency

@CL3

f

CK3

166

143

MHz

t

CK3

67ns

t

AC3

5.4

5.4

ns

@CL2

t

CK2

7.5

7.5

ns

t

AC2

5.4

5.4

ns