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HYB18T512160BF-25F Datasheet(PDF) 8 Page - Qimonda AG |
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HYB18T512160BF-25F Datasheet(HTML) 8 Page - Qimonda AG |
8 / 68 page Internet Data Sheet Rev. 1.1, 2007-05 8 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM 2 Chip Configuration This chapter contains the chip configuration and addressing. 2.1 Chip Configuration The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball# and Buffer Type columns are explained in Table 8 and Table 9 respectively. The ball numbering for the FBGA package is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16. TABLE 7 Chip Configuration of DDR2 SDRAM Ball# Name Ball Type Buffer Type Function Clock Signals ×4/×8 organization E8 CK I SSTL Clock Signal CK, Complementary Clock Signal CK F8 CK I SSTL F2 CKE I SSTL Clock Enable Clock Signals ×16 organization J8 CK I SSTL Clock Signal CK, Complementary Clock Signal CK Note: See functional description in x4/x8 organization K8 CK I SSTL K2 CKE I SSTL Clock Enable Note: See functional description in x4/x8 organization Control Signals ×4/×8 organizations F7 RAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) G7 CAS I SSTL F3 WE I SSTL G8 CS I SSTL Chip Select Control Signals ×16 organization K7 RAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) L7 CAS I SSTL K3 WE I SSTL L8 CS I SSTL Chip Select Address Signals ×4/×8 organizations G2 BA0 I SSTL Bank Address Bus 1:0 G3 BA1 I SSTL |
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