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HYS64T256020EDL Datasheet(PDF) 6 Page - Qimonda AG |
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HYS64T256020EDL Datasheet(HTML) 6 Page - Qimonda AG |
6 / 51 page Internet Data Sheet Rev. 1.0, 2007-03 6 11212006-D34H-5W6Z HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module 2 Pin Configuration The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted in Figure 1. TABLE 5 Pin Configuration of SO-DIMM Pin No. Name Pin Type Buffer Type Function Clock Signals 30 CK0 I SSTL Clock Signals 2:0, Complement Clock Signals 2:0 164 CK1 I SSTL 32 CK0 ISSTL 166 CK1 ISSTL 79 CKE0 I SSTL Clock Enable Rank 1:0 Note: 2 Ranks module 80 CKE1 I SSTL NC NC — Not Connected Note: 1-rank module Control Signals 110 S0 ISSTL Chip Select Rank 1:0 Note: 2 Ranks module 115 S1 ISSTL NC NC — Not Connected Note: 1-rank module 108 RAS ISSTL Row Address Strobe 113 CAS ISSTL Column Address Strobe 109 WE ISSTL Write Enable Address Signals 107 BA0 I SSTL Bank Address Bus 2:0 106 BA1 I SSTL 85 BA2 I SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS NC NC SSTL Less than 1Gb DDR2 SDRAMS |
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