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GL830 Datasheet(PDF) 19 Page - GENESYS LOGIC

Part # GL830
Description  USB 2.0 to SATA Bridge Controller
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL830 Datasheet(HTML) 19 Page - GENESYS LOGIC

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GL830 USB2.0 to SATA Bridge Controller
©2007 Genesys Logic Inc. - All rights reserved.
Page 19
V5
52
p
5V Power Input
ATA/ ATAPI Interface (Host mode)
Pin Name
Pin#
Type
Description
DD0~15
44,40,36,
30,26,14,
10,6,8,12,
21,28,32,
38,42,46
B
IDE Data Bus
ARESET_
127
I
(pu)
Device Reset
CS1_, CS0_
85, 83
I
(pu)
Chip Select #1,#0
DA0~2
79,78,81
I
(pd)
IDE Address #2,#1,#0
INTRQ
65
O
IDE interrupt input
DMACK_
62
I
(pu)
IDE Acknowledge
IORDY
60
O
IDE Ready
DIOR_
58
I
(pu)
IDE read signal
DIOW_
56
I
(pu)
IDE write signal
DMARQ
54
O
IDE request
ATA/ ATAPI Interface (Device mode)
Pin Name
Pin#
Type
Description
DD0~15
44,40,36,
30,26,14,
10,6,8,12,
21,28,32,
38,42,46
B
IDE Data Bus
ARESET_
127
O
Device Reset
CS1_, CS0_
85, 83
O
Chip Select #1,#0
DA0~2
79,78,81
O
IDE Address #2,#1,#0
INTRQ
65
I
(pd)
IDE interrupt input
DMACK_
62
O
IDE Acknowledge
IORDY
60
I
(pu)
IDE Ready
DIOR_
58
O
IDE read signal
DIOW_
56
O
IDE write signal
DMARQ
54
I
(pd)
IDE request


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