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GL9714 Datasheet(PDF) 43 Page - GENESYS LOGIC |
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GL9714 Datasheet(HTML) 43 Page - GENESYS LOGIC |
43 / 46 page GL9714 PCI Express TM PIPE x4 PHY ©2004-2007 Genesys Logic Inc. - All rights reserved. Page 43 Table 8.2 – Input Setup, Hold Time and Output Timing for 8-bit DDR Mode Symbol Parameter Min Typ Max Unit TCYCLE PCLK cycle time 7.98 8 8.02 ns Duty-H Duty cycle for PCLK high 48 - 50 % TIS Input setup time - - 1.4 ns TIH Input hold time 0.5 - - ns TCO Clock to output delay - 1.5 1.6 ns TOH Output hold time 0.8 1 - ns Note: This table is based on design target, correlation data will be posted later. Table 8.3 – Input Setup, Hold Time and Output Timing for 16-bit Mode Symbol Parameter Min Typ Max Unit TCYCLE PCLK cycle time 7.98 8 8.02 ns Duty-H Duty cycle for PCLK high 48 - 50 % TIS Input setup time - - 1.4 ns TIH Input hold time 0.5 - - ns TCO Clock to output delay - 5.3 5.6 ns TOH Output hold time 4.3 4.7 - ns Note: This table is based on design target, correlation data will be posted later. Table 8.4 – Input Setup, Hold Time and Output Timing for 10-bit SDR Mode Symbol Parameter Min Typ Max Unit TCYCLE PCLK cycle time 3.99 4 4.01 ns Duty-H Duty cycle for PCLK high 35 - 50 % TIS Input setup time - - 1 ns TIH Input hold time 1 - - ns TCO Clock to output delay - 4 4.2 ns TOH Output hold time 3.4 3.7 - ns Note: This table is based on design target, correlation data will be posted later. |
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