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AK5701 Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AK5701 Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
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4 / 40 page  ASAHI KASEI [AKD5701-A] <KM076904> 2006 / 06 - 4 - (2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) *Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 GND GND NC NC SDTO VD EXSDTI EXLRCK EXBCLK MCKI a) Set up jumper pins of MCKI clock X’tal of 11.2896MHz (Default) is set on the AKD5701-A. In this case, the AK5701 corresponds to PLL reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5701 is supplied to a divider (U3: 74VHC4040), EXBCLK and LRCK clocks are generated by the divider. Then “MCKO bit” in the AK5701 should be set to “1”. When an external clock is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on JP16 (XTI) and select EXTCLK/BCLK on JP17 (MCLK_SEL). JP14 (EXT1) and R20 should be properly selected in order too match the output impedance of the clock generator. JP16 XTI JP19 MCLK_SEL MCKI JP11 MKFS EXTCLK /BCLK 5701- MCKO EXTCLK /BCLK 4114- MCKO 256fs 512fs 1024fs MCKO b) Set up jumper pins of BCLK clock JP12 BCLK 32fs 16fs 64fs EXT JP17 BCLK_SEL BCLK/ DIT EXTBCLK/ DIT EXT BCLK c) Set up jumper pins of LRCK clock JP13 LRCK 1fs 2fs EXT JP18 LRCK_SEL LRCK/ DIT EXTLRCK/ DIT EXT LRCK |
Similar Part No. - AK5701 |
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Similar Description - AK5701 |
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