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ST72P63BE1M1 Datasheet(PDF) 45 Page - STMicroelectronics

Part No. ST72P63BE1M1
Description  Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I²C
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST72P63BE1M1 Datasheet(HTML) 45 Page - STMicroelectronics

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12.2 16-bit timer
12.2.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
12.2.2 Main features
Programmable prescaler: f
CPU divided by 2, 4 or 8
Overflow status flag and maskable interrupt
External clock input (must be at least four times
slower than the CPU clock speed) with the choice
of active edge
1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Pulse width modulation mode (PWM)
One Pulse mode
Reduced Power mode
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The block diagram is shown in Figure 27.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
12.2.3 Functional description
12.2.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high and low.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
m
ost significant byte (MS byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS
byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 18,
"Clock Control Bits". The value in the counter reg-
ister repeats every 131072, 262144 or 524288
CPU clock cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
or an external frequency.


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