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ST72P63BE1M1 Datasheet(PDF) 86 Page - STMicroelectronics

Part No. ST72P63BE1M1
Description  Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I²C
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST72P63BE1M1 Datasheet(HTML) 86 Page - STMicroelectronics

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12.5 I²C bus interface (I²C)
12.5.1 Introduction
The I²C Bus Interface serves as an interface be-
tween the microcontroller and the serial I²C bus. It
provides both multimaster and slave functions,
and controls all I²C bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast I²C
mode (400 kHz).
12.5.2 Main features
Parallel-bus/I²C protocol converter
Multi-master capability
7-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
I²C master features:
Clock generation
I²C bus busy flag
Arbitration Lost flag
End of byte transmission flag
Transmitter/Receiver flag
Start bit detection flag
Start and Stop generation
I²C slave features:
Stop bit detection
I²C bus busy flag
Detection of misplaced start or stop condition
Programmable I²C Address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
12.5.3 General description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I²C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I²C bus
and a Fast I²C bus. This selection is made by soft-
ware.
Mode selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7-bit), and the General Call
address. The General Call address detection may
be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 43.
Figure 43. I²C bus protocol
SCL
SDA
12
8
9
MSB
ACK
STOP
START
CONDITION
CONDITION
VR02119B


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