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ST72P63BE1M1 Datasheet(PDF) 83 Page - STMicroelectronics |
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ST72P63BE1M1 Datasheet(HTML) 83 Page - STMicroelectronics |
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ST7263BDx ST7263BHx ST7263BKx ST7263BE 83/145 USB INTERFACE (Cont’d) Endpoint n Register B (EPnRB) Read / Write Reset value: 0000 xxxx (0xh) These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and register map). Bit 7 = CTRL Control. This bit should be 0. Note: If this bit is 1, the Endpoint is a control end- point. (Endpoint 0 is always a control Endpoint, but it is possible to have more than one control End- point). Bit 6 = DTOG_RX Data toggle, for reception trans- fers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP trans- actions start always with DATA0 PID). The receiv- er toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the end- point status, which are listed below: These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SET- UP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. Bits 3:0 = EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”. Endpoint 0 Register B (EP0RB) Read / Write Reset value: 1000 0000 (80h) This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus re- set. Bit 7 = Forced by hardware to 1. Bits 6:4 = Refer to the EPnRB register for a de- scription of these bits. Bits 3:0 = Forced by hardware to 0. 70 CTRL DTOG _RX STAT _RX1 STAT _RX0 EA3 EA2 EA1 EA0 STAT_RX1 STAT_RX0 Meaning 00 DISABLED: reception transfers cannot be exe- cuted. 01 STALL: the endpoint is stalled and all reception requests result in a STALL handshake. 10 NAK: the endpoint is na- ked and all reception re- quests result in a NAK handshake. 11 VALID: this endpoint is enabled for reception. 70 1 DTOG RX STAT RX1 STAT RX0 00 0 0 STAT_RX1 STAT_RX0 Meaning |
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