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ST72P63BE1M1 Datasheet(PDF) 76 Page - STMicroelectronics

Part No. ST72P63BE1M1
Description  Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I²C
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST72P63BE1M1 Datasheet(HTML) 76 Page - STMicroelectronics

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Serial communication interface (Cont’d)
Data Register (SCIDR)
Read/Write
Reset value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 38).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 38).
Baud Rate Register (SCIBRR)
Read/Write
Reset value: 0000 0000 (00h)
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock.
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
70
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
PR prescaling factor
SCP1
SCP0
10
0
30
1
41
0
13
1
1
TR dividing factor
SCT2
SCT1
SCT0
10
0
0
20
0
1
40
1
0
80
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
RR dividing factor
SCR2
SCR1
SCR0
10
0
0
20
0
1
40
1
0
80
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
PR prescaling factor
SCP1
SCP0


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