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T15M1024A-100NI Datasheet(PDF) 8 Page - Taiwan Memory Technology |
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T15M1024A-100NI Datasheet(HTML) 8 Page - Taiwan Memory Technology |
8 / 13 page TE CH tm T15M1024A TM Technology Inc. reserves the right P. 8 Publication Date: OCT. 2004 to change products or specifications without notice. Revision:C WRITE CYCLE 1 ( WE Controlled) WRITE CYCLE 2 ( CE Controlled) NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low 1 CE , a high CE2 and a low WE . A write begins at the lateat transition among 1 CE goes low, CE2 going high and WE going low. A write end at the earliest transition among 1 CE going high, CE2 going low and WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of 1 CE going low or CE2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WC tWHZ tDW D IN tDH tWR tAS tWP Ad d r es s CE 2 CE 1 WE D OU T tAW tCW tOW Hig h-Z Hi g h - Z DO N' T CA R E U NDE F I NE D t WC tDW D IN tDH t WR t AS t WP t CW Ad d r es s CE 1 WE D OU T CE 2 t AW H i gh- Z H i gh- Z Hi g h - Z |
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