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KSZ8842-16 Datasheet(PDF) 5 Page - Micrel Semiconductor |
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KSZ8842-16 Datasheet(HTML) 5 Page - Micrel Semiconductor |
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5 / 126 page  Micrel Confidential KSZ8842-16/32 MQL/MVL November 2005 5 Rev. 1.4 Bus Interface Unit (BIU)......................................................................................................... 30 Asynchronous Interface ....................................................................................................................................................32 Synchronous Interface ......................................................................................................................................................33 Summary ..........................................................................................................................................................................33 BIU Implementation Principles ..........................................................................................................................................34 Queue Management Unit (QMU) ........................................................................................... 35 Transmit Queue (TXQ) Frame Format..............................................................................................................................35 Receive Queue (RXQ) Frame Format ..............................................................................................................................36 Advanced Switch Functions ................................................................................................. 38 Spanning Tree Support.....................................................................................................................................................38 IGMP Support ...................................................................................................................................................................39 “IGMP” Snooping............................................................................................................................................................ 39 “Multicast Address Insertion” in the Static MAC Table.................................................................................................... 39 IPv6 MLD Snooping ..........................................................................................................................................................39 Port Mirroring Support.......................................................................................................................................................39 IEEE 802.1Q VLAN Support .............................................................................................................................................40 QoS Priority Support .........................................................................................................................................................40 Port-Based Priority............................................................................................................................................................40 802.1p-Based Priority .......................................................................................................................................................40 DiffServ based Priority ......................................................................................................................................................41 Rate Limiting Support .......................................................................................................................................................41 MAC Filtering Function .....................................................................................................................................................42 Configuration Interface......................................................................................................................................................42 EEPROM Interface ...........................................................................................................................................................42 Loopback Support.............................................................................................................................................................43 Far-end Loopback .......................................................................................................................................................... 43 Near-end (Remote) Loopback ........................................................................................................................................ 43 CPU Interface I/O Registers .................................................................................................. 45 I/O Registers .....................................................................................................................................................................45 Internal I/O Space Mapping ..............................................................................................................................................46 Register Map: Switch & MAC/PHY........................................................................................ 54 Bit Type Definition.............................................................................................................................................................54 Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)......................................................................54 Bank 0 Base Address Register (0x00): BAR.....................................................................................................................54 Bank 0 Bus Error Status Register (0x06): BESR ..............................................................................................................55 Bank 0 Bus Burst Length Register (0x08): BBLR .............................................................................................................55 Bank 1: Reserved .............................................................................................................................................................55 Bank 2 Host MAC Address Register Low (0x00): MARL ..................................................................................................55 Bank 2 Host MAC Address Register Middle (0x02): MARM .............................................................................................56 Bank 2 Host MAC Address Register High (0x04): MARH .................................................................................................56 Bank 3 On-Chip Bus Control Register (0x00): OBCR .......................................................................................................56 Bank 3 EEPROM Control Register (0x02): EEPCR ..........................................................................................................57 Bank 3 Memory BIST INFO Register (0x04): MBIR ..........................................................................................................57 Bank 3 Global Reset Register (0x06): GRR......................................................................................................................57 Bank 3 Bus Configuration Register (0x08): BCFG ............................................................................................................58 Banks 4—15: Reserved ....................................................................................................................................................58 Bank 16 Transmit Control Register (0x00): TXCR ............................................................................................................58 Bank 16 Transmit Status Register (0x02): TXSR..............................................................................................................58 Bank 16 Receive Control Register (0x04): RXCR.............................................................................................................59 Bank 16 TXQ Memory Information Register (0x08): TXMIR .............................................................................................59 Bank 16 RXQ Memory Information Register (0x0A): RXMIR............................................................................................60 Bank 17 TXQ Command Register (0x00): TXQCR ...........................................................................................................60 Bank 17 RXQ Command Register (0x02): RXQCR ..........................................................................................................60 Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR .............................................................................................60 Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR ............................................................................................61 Bank 17 QMU Data Register Low (0x08): QDRL ..............................................................................................................61 Bank 17 QMU Data Register High (0x0A): QDRH ............................................................................................................61 Bank 18 Interrupt Enable Register (0x00): IER .................................................................................................................62 Bank 18 Interrupt Status Register (0x02): ISR ..................................................................................................................63 Bank 18 Receive Status Register (0x04): RXSR ..............................................................................................................64 |
Similar Part No. - KSZ8842-16 |
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Similar Description - KSZ8842-16 |
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