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AK4634 Datasheet(PDF) 56 Page - Asahi Kasei Microsystems |
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AK4634 Datasheet(HTML) 56 Page - Asahi Kasei Microsystems |
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56 / 77 page  [AK4634] Rev. 0.5 2007/10 - 56 - ■ Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written and read by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. Data writing is valid on the rising edge of the 16th CCLK after the falling edge of CSN. CSN should be set to “H” every after a data writing for each address. In reading operation, the CDTIO pin changes to output mode at the falling edge of 8th CCLK and outputs D7-D0. The output finishes on the rising edge of CSN. However this reading function is available only at READ bit = “1”. When READ bit = “0”, the CDTIO pin stays as Hi-Z even after the falling edge of 8th CCLK. The CDTIO pin is placed in a Hi-Z state except outputting data at read operation mode. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at the PDN pin = “L”. Note 38. It is available for reading the address 00H ~ 11H, 20H ~ 24H and 30H. When reading the address 12H ~ 1FH, 25H ~ 2F and 31H ~ 4FH, the register values are invalid. CSN CCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CDTIO A6 A5 A2 A3 A1 A0 A4 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W: READ/WRITE (“1”: WRITE, “0”: READ) A6-A0: Register Address D7-D0: Control data Clock, “H” or “L” Clock, “H” or “L” “H” or “L” “H” or “L” Figure 47. Serial Control I/F Timing |
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