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AK4631 Datasheet(PDF) 66 Page - Asahi Kasei Microsystems |
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AK4631 Datasheet(HTML) 66 Page - Asahi Kasei Microsystems |
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66 / 69 page  ASAHI KASEI [AK4631] MS0317-E-01 2004/11 - 66 - Stop of Clock Master clock can be stopped when ADC, DAC, ALC1, ALC2 and IPGA don’t operate. 1. In case of PLL Master Mode MCKPD bit (Addr:01H,D2) External MCKI PMPLL bit (Addr:01H,D0) MCKO bit (Addr:01H,D1) Input (4) (1) (2) (3) "H"or"L" Example: Audio I/F Format: DSP Mode, BCKP = MSBS = “0” BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Sampling Frequency:8kHz Stop an external MCKI (1) (2) (3) Addr:01H, Data:0CH Figure 52. Clock Stopping Sequence (1) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO clock: MCKO bit = “1” → “0” (3) Pull down the MCKI pin: MCKPD bit = “0” → “1” When the external master clock becomes Hi-Z, MCKI pin should be pulled down. (4) Stop an external master clock. 2. When an external clocks (FCK or BICK pins) are used in PLL Slave Mode. External BICK PMPLL bit (Addr:01H,D0) Input (1) (2) External FCK Input (2) Example Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) Addr:01H, Data:04H (2) Stop the external clocks Figure 53. Clock Stopping Sequence (2) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop the external BICK and FCK clocks |
Similar Part No. - AK4631_1 |
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Similar Description - AK4631_1 |
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