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AKD4368 Datasheet(PDF) 5 Page - Asahi Kasei Microsystems |
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AKD4368 Datasheet(HTML) 5 Page - Asahi Kasei Microsystems |
5 / 60 page ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 5 - PIN/FUNCTION No. Pin Name I/O Function B1 MCKO O Master Clock Output C2 DVSS - Digital Ground C1 DVDD - Digital Power Supply D2 I2C I Control Mode Select “H”: I 2C Bus, “L”: 3-wire Serial D1 MCKI I Master Clock Input E2 LRCK I/O L/R Clock This clock determines which audio channel is currently being input on SDATA pin. E1 BICK I/O Serial Bit Clock This clock is used to latch audio data. F2 SDATA I Audio Serial Data Input SDA I/O Control Data Input/Output (I2C pin = “H”) F1 CDTI I Control Data Input (I2C pin = “L”) SCL I Control Data Clock (I2C pin = “H”) G2 CCLK I Control Data Clock (I2C pin = “L”) CAD0 I Chip Address 0 Select (I2C pin = “H”) G3 CSN I Control Data Chip Select (I2C pin = “L”) F4 PDN I Power-down & Reset When “L”, the AK4368 is in power-down mode and is held in reset. The AK4368 should always be reset upon power-up. G5 3DCAP1 O Capacitor Connect Pin 1 for 3D Stereo Enhancement Connected to 3DCAP2 pin with 4.7nF capacitor in series. F6 3DCAP2 O Capacitor Connect Pin 2 for 3D Stereo Enhancement Connected to 3DCAP1 pin with 4.7nF capacitor in series and connected to 3DCAP3 pin with 470nF capacitor in series. G6 3DCAP3 O Capacitor Connect Pin 1 for 3D Stereo Enhancement Connected to 3DCAP2 pin with 470nF capacitor in series. F7 LOUT O Lch Analog Output E6 ROUT O Rch Analog Output E7 VCOM O Common Voltage Output Normally connected to AVSS pin with a 2.2 µF electrolytic capacitor. D7 AVDD - Analog Power Supply C6 AVSS - Analog Ground D6 MUTET O Mute Time Constant Control Connected to AVSS pin with a capacitor for mute time constant. C7 HVDD - Power Supply Pin for Headphone Amp B6 HVSS - Ground for Headphone Amp B7 HPR O Rch Headphone Amp Output A6 HPL O Lch Headphone Amp Output A5 MIN I Mono Analog Input A4 RIN I Rch Analog Input B3 LIN I Lch Analog Input A3 VCOC O Output for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and one capacitor in series. B2 PVSS - Ground for PLL. Connected to AVSS. A2 PVDD - Power Supply for PLL. Normally connected to AVDD. |
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