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AK4254 Datasheet(PDF) 7 Page - Asahi Kasei Microsystems |
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AK4254 Datasheet(HTML) 7 Page - Asahi Kasei Microsystems |
7 / 22 page ASAHI KASEI [AK4254] MS0586-E-01 2007/08 - 7 - SWITCHING CHARACTERISTICS (Ta =-40 ∼85°C; AVDD=CVDD1=CVDD2=2.7V∼3.6V; CL = 20pF) Parameter Symbol Min typ max Units Control Interface Timing (3-wire Serial mode) PDN “ ↑” to CSN “↓” CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “ ↓” to CCLK “↑” CCLK “ ↑” to CSN “↑” tPDCS tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 150 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency PDN “ ↑” to SDA “↓” @SCL = “H” Bus Free Time Between Transmissions Start Condition Hold Time (Prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note: 10) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tPDSD tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb - 1.3 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - - 0.3 0.3 - 50 400 kHz μs μs μs μs μs μs μs μs μs μs μs ns pF Reset Timing PDN Pulse Width (Note: 11) tPD 150 ns Note: 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 11. In Serial Control Mode (P/S pin= “L”), it is recommended that the AK4254 is powered up at the PDN pin=“L”. In Parallel Control Mode, resetting by the PDN pin = “L” is not needed when power up. Note: 12. I2C is a registered trademark of Philips Semiconductors. |
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