1.

General description

The 74AUP1G74 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

This device ensures a very low static and dynamic power consumption across the entire

the device when it is powered down.

The 74AUP1G74 provides the single positive-edge triggered D-type flip-flop with

individual data (D) input, clock (CP) input, set (SD) and reset (RD) inputs and

complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs

and operate independently of the clock input. Information on the data input is transferred

to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be

stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

2.

Features

74AUP1G74

Low-power D-type flip-flop with set and reset; positive-edge

trigger

Rev. 01 — 25 August 2006

Product data sheet