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CD54HC173 Datasheet(PDF) 1 Page - Texas Instruments

Part No. CD54HC173
Description  High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD54HC173 Datasheet(HTML) 1 Page - Texas Instruments

 
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Data sheet acquired from Harris Semiconductor
SCHS158E
Features
• Three-State Buffered Outputs
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD54HC173, CD54HCT173
(CERDIP)
CD74HC173
(PDIP, SOIC, SOP, TSSOP)
CD74HCT173
(PDIP, SOIC)
TOP VIEW
Description
The ’HC173 and ’HCT173 high speed three-state quad D-
type flip-flops are fabricated with silicon gate CMOS technol-
ogy. They possess the low power consumption of standard
CMOS Integrated circuits, and can operate at speeds com-
parable to the equivalent low power Schottky devices. The
buffered outputs can drive 15 LSTTL loads. The large output
drive capability and three-state feature make these parts ide-
ally suited for interfacing with bus lines in bus oriented sys-
tems.
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
The ’HCT173 logic family is functionally, as well as pin com-
patible with the standard LS logic family
.
OE
OE2
Q0
Q1
Q2
Q3
GND
VCC
MR
D0
D1
D2
D3
E2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
E1
CP
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC173F3A
-55 to 125
16 Ld CERDIP
CD54HCT173F3A
-55 to 125
16 Ld CERDIP
CD74HC173E
-55 to 125
16 Ld PDIP
CD74HC173M
-55 to 125
16 Ld SOIC
CD74HC173MT
-55 to 125
16 Ld SOIC
CD74HC173M96
-55 to 125
16 Ld SOIC
CD74HC173NSR
-55 to 125
16 Ld SOP
CD74HC173PW
-55 to 125
16 Ld TSSOP
CD74HC173PWR
-55 to 125
16 Ld TSSOP
CD74HC173PWT
-55 to 125
16 Ld TSSOP
CD74HCT173E
-55 to 125
16 Ld PDIP
CD74HCT173M
-55 to 125
16 Ld SOIC
CD74HCT173MT
-55 to 125
16 Ld SOIC
CD74HCT173M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC173, CD74HC173,
CD54HCT173, CD74HCT173
High-Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
Quad D-
Type


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